Today, microprocessor systems with a local display device such as a liquid-crystal display may use a discrete graphics chip or an integrated graphics engine (commonly called a GPU) built into a core-logic chip such as a north bridge or south bridge.
FIG. 1 is a diagram of a first conventional microprocessor system 10. The microprocessor system 10 comprises a processor 12 coupled to a south bridge 14. The processor 12 includes one or more processor cores 15, a DRAM controller 16, both of which are coupled to a bus 20. The bus 20 is coupled to a first bus interface 22. The DRAM controller 16 can be coupled to a DRAM 24. The south bridge 14 communicates with the processor 12, via a second bus interface 26 to the first bus interface 22. The south bridge 14 includes a second bus 28, which is coupled to a plurality of input-output (I/O) devices 30-40.
The second bus interface 26 communicates with a graphics engine external 42 to the south bridge 14, which can be coupled to a display 44 and a second memory 46.
FIG. 2 is a second conventional microprocessor system 10′, in which similar elements have similar numbers to FIG. 1. In FIG. 2, the integrated graphics engine 42′ is internal to the south bridge 14′ and is coupled to a display 44′.
The integrated solution of FIG. 3 usually shares the system's main memory 24′ between the processor core 15′ and the graphics engine 42′, an approach known as Unified Memory Architecture (UMA). Sometimes, especially in upgraded systems, both discrete and integrated solutions are present at the same time. The graphics engine 42′ 4111P has an associated display interface on the same chip, such as RGB or DVI so some systems have two interfaces when only one is needed.
In UMA systems that have the main memory interface, integrated into the microprocessor, the integrated-graphics solution requires display refresh data to be transferred from the memory 24 to the processor core 15 via the memory bus, then from the processor 12 to the graphics engine 42 in the south bridge 14 via a front-side bus. This extra transfer wastes energy and reduces system performance by consuming some of the bandwidth of the front-side bus.
In some systems, the graphics engine 42 is integrated into the microprocessor chip. FIG. 3 is a third conventional microprocessor system 10″ in which similar elements have similar numbers as in FIG. 1. In FIG. 3, the graphics engine 42″ is part of the processor 12″.
A fully integrated UMA solution such as that above is acceptable for low-end systems, but not for mid-range or high-end systems. Modern processor cores are already large and expensive to manufacture, and a good graphics engine is just as large and complex as a processor core. Combining both a processor core and a graphics engine on one chip imposes an unacceptably high cost penalty. Accordingly what is desired is a microcomputer that overcomes the above-mentioned issues. The present invention addresses such a need.